Titlebook: VLSI-SoC: Technologies for Systems Integration; 17th IFIP WG 10.5/IE Jürgen Becker,Marcelo Johann,Ricardo Reis Conference proceedings 2011

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Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow An the Context-Adaptive Binary Arithmetic Decoder (CABAD), as used in the H.264/AVC on-chip video decoders. We propose and implement a new approach for accelerating the decoding hardware of the significance map by providing the correct context for the regular hardware engine of the (CABAD). The design

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From Assertion-Based Verification to Assertion-Based Synthesis, with specific components to obtain a design that is correct by construction. It shortens the design flow by removing implementation and functional verification steps. Our approach synthesizes circuits specified by hundreds of temporal properties in a few seconds. Complex examples (.. and GenBuf) show the efficiency of the approach.