Titlebook: VLSI-SoC: Technologies for Systems Integration; 17th IFIP WG 10.5/IE Jürgen Becker,Marcelo Johann,Ricardo Reis Conference proceedings 2011

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Crosstalk Fault Tolerant NoC: Design and Evaluation,ut also affect the reliability of these components. Chip-level global buses are especially subject to crosstalk faults, which can lead to increased delay and glitches. This paper evaluates different crosstalk fault tolerant approaches for Networks-on-chip (NoCs) links such that the network can maint

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DALLY

Power Macro-Modeling Using an Iterative LS-SVM Method,r estimation. The basic approach is first to obtain the power consumption of the module for a large number of points in the input signal space. Least-Squares SVMs are then used to compute the best model to fit this set of points. We have performed extensive experiments in order to determine the best

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Enhancing Electromagnetic Attacks Using Spectral Coherence Based Cartography,ar mathematically speaking, Power or Electromagnetic Attacks have different advantages in practice. Among the advantages of EM attacks, the feasibility of attacking limited and bounded area of integrated systems is the key one. However, efficient techniques are required to localize hot spots, charac

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A Multistep Extrapolated S-Parameter Model for Arbitrary On-Chip Interconnect Structures,mmunication structures, such as hierarchical bus architectures and networks-on-chip. In this chapter we introduce a computationally-efficient wide-bandwidth characterization method based on an incremental extrapolation of S-parameters for arbitrary interconnect structures. Our method defines a syste