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Titlebook: Minimizing and Exploiting Leakage in VLSI Design; Nikhil Jayakumar,Suganth Paul,Sunil P. Khatri Book 2010 Springer-Verlag US 2010 ASIC.EDA

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書目名稱Minimizing and Exploiting Leakage in VLSI Design
編輯Nikhil Jayakumar,Suganth Paul,Sunil P. Khatri
視頻videohttp://file.papertrans.cn/635/634623/634623.mp4
概述Provides a variety of approaches to control and exploit leakage.Examines the issues with implementing sub-threshold logic and describes techniques to tackle these issues.Presents a new, practical self
圖書封面Titlebook: Minimizing and Exploiting Leakage in VLSI Design;  Nikhil Jayakumar,Suganth Paul,Sunil P. Khatri Book 2010 Springer-Verlag US 2010 ASIC.EDA
描述.Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic..
出版日期Book 2010
關(guān)鍵詞ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; V
版次1
doihttps://doi.org/10.1007/978-1-4419-0950-3
isbn_softcover978-1-4899-8529-3
isbn_ebook978-1-4419-0950-3
copyrightSpringer-Verlag US 2010
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https://doi.org/10.1007/978-1-4419-0950-3ASIC; EDA; Electronic Design Automation; Leakage; Low Power Design; Sub-threshold logic; Transistor; VLSI; V
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978-1-4899-8529-3Springer-Verlag US 2010
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e second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic..978-1-4899-8529-3978-1-4419-0950-3
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Self-Competitive Neural NetworksNN tries to improve its accuracy by competing with itself (generating hard samples and then learning them), the technique is called Self-Competitive Neural Network (SCNN). To generate such samples, we pose the problem as an optimization task, where the network weights are fixed and use a gradient de
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