Titlebook: Defect and Fault Tolerance in VLSI Systems; Volume 2 C. H. Stapper,V. K. Jain,G. Saucier Book 1990 Springer Science+Business Media New York

腐敗

PACK

https://doi.org/10.1007/978-3-319-49823-2computational abilities envisioned a new breed of integrated circuits that could implement such systems and would be much less sensitive to element failure than present day computers. Analog VLSI is a technology suitable for the implementation of synthetic neural systems [2, 3] on silicon.

GRILL

模范

Intend

A Unified Approach to Yield Analysis of Defect Tolerant CircuitsConsequently, models for yield analysis have been proposed for “l(fā)arge area clustering” and “small area clustering”. By adding a new parameter, the ., to the existing parameters of the defect distribution we unify the analysis of the existing models and at the same time add a whole range of “medium s

訓(xùn)誡

發(fā)炎

Fault-Tolerant k-out-of-n Logic Unit Network with Minimum Interconnection-out-of-n, k < n, unit group, called a block, is operated with k units being worked in the normal operation and the remaining (n-k) units being used as spares. The n switching parts in the block, instead of the traditional k ones, can also mask the faults in the switching part of the block. Under th

GROWL

Extended Duplex Fault Tolerant System With Integrated Control Flow Checkingrchitectures are often used in highly dependable systems. However, these architectures have several drawbacks for onboard equipments: cost, weight, volume, power consumption and dissipation often lead to difficult problems. In other respects, if duplex architectures allow to reduce some of these pro

高歌

可憎

An Integer Linear Programming Approach to General Fault Covering Problems reconfigurable chips in which there are redundant elements that can be used to replace the defective elements. The fault covering problem is to assign redundant elements to replace the defective elements such that the chip will function properly. A general formulation to represent the relationship