Titlebook: Algorithms for VLSI Physical Design Automation; Naveed A. Sherwani Book 1993 Springer Science+Business Media New York 1993 Phase.VLSI.auto

MOTIF

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Darstellung nach Begriffsinhaltenuce the possibility of fabrication errors, reduce the total chip area and therefore, improve performance. In this chapter, we will discuss two methods of improving detailed routing: via minimization and over-the-cell routing.

PRISE

Darstellung nach Begriffsinhalten proportional to clock frequency. Clock nets need to be routed with great precision, since the actual length of the path of a net from its entry point to its terminals determines the maximum clock frequency on which a chip may operate. A clock router needs to take several factors into account, inclu