Titlebook: Algorithms for VLSI Physical Design Automation; Naveed A. Sherwani Book 1993 Springer Science+Business Media New York 1993 Phase.VLSI.auto

FIS

誘使

Directed

Zusammenfassung der Untersuchungsergebnisse,require further partitioning. Thus, partitioning can be used in a hierarchical manner until each subsystem is of manageable size. Partitioning is a general technique and is used in diverse areas. For example, in algorithm design, the . approach is routinely used to partition complex problems into sm

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Zusammenfassung der Untersuchungsergebnisse,otal wire length. For high performance chips, total wire length may not be a major concern. Instead, we may want to minimize the longest wire to minimize the delay in the wire and therefore maximize its performance. Usually routing involves special treatment of such nets as clock nets, power and gro

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Darstellung nach Begriffsinhaltenity and the total area consumed make it necessary to develop special routers for power and ground nets. In this chapter, we will discuss the problems associated with clock, power and ground routing and present the basic routing algorithms for these special nets.

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坦白

hich is useful forfinding advanced material on a topic. ..Algorithms for VLSI Physical Design Automation. is an invaluablereference for professionals in layout, design automation and physicaldesign. .978-1-4757-2221-5978-1-4757-2219-2

Conclave

Design and Fabrication of VLSI Devices,other layer. After patterning of all the layers, the wafer is cut into individual chips and packaged. Thus, the VLSI physical design is a process of creating all the necessary masks that define the sizes and location of the various devices and the interconnections between them.

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