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Titlebook: VLSI-SoC: Research Trends in VLSI and Systems on Chip; Fourteenth Internati Giovanni Micheli,Salvador Mir,Ricardo Reis Conference proceedin

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樓主: patch-test
51#
發(fā)表于 2025-3-30 08:43:00 | 只看該作者
52#
發(fā)表于 2025-3-30 14:09:52 | 只看該作者
Library Compatible Variational Delay Computation,ing concern. Process variations have immediate impact on circuit performance and behavior and standard design and signoff methodologies have to account for such variability. In this context, timing verification, already a challenging task due to the sheer complexity of todays designs, becomes an inc
53#
發(fā)表于 2025-3-30 19:36:21 | 只看該作者
54#
發(fā)表于 2025-3-30 21:05:53 | 只看該作者
Frequency and Speed Setting for Energy Conservation in Autonomous Mobile Robots,ivors after a disaster. Mobile robots usually carry limited energy (mostly rechargeable batteries) so energy conservation is crucial. In a mobile robot, the processor and the motors are two major energy consumers. While a robot is moving, it has to detect an obstacle before a collision. This results
55#
發(fā)表于 2025-3-31 02:16:40 | 只看該作者
Configurable On-Line Global Energy Optimization in Multi-Core Embedded Systems Using Principles of encies of multiple processing elements (PE), tailored to the instantaneous workload information and is fully adaptive to variations in process and temperature. The circuit design borrows some of the basic principles of analog computation to continuously optimize the system-wide energy dissipation of
56#
發(fā)表于 2025-3-31 05:41:47 | 只看該作者
57#
發(fā)表于 2025-3-31 11:20:51 | 只看該作者
58#
發(fā)表于 2025-3-31 14:33:18 | 只看該作者
CAT Platform for Analogue and Mixed-Signal Test Evaluation and Optimization,its. The CAT platform, integrated in the Cadence Design Framework Environment, includes tools for fault simulation, test generation and test optimization for these types of circuits. Fault modeling and fault injection are simulator independent, which makes this approach flexible with respect to past
59#
發(fā)表于 2025-3-31 20:58:17 | 只看該作者
Broadside Transition Test Generation for Partial Scan Circuits through Stuck-at Test Generation,t of a given partial scan circuit into some combinational circuits. Then, by performing stuck-at test generation on the transformed circuits, broadside transition tests for the original circuit are obtained. This method allows us to use existing stuck-at test generation tools in order to generate br
60#
發(fā)表于 2025-3-31 22:34:22 | 只看該作者
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