Titlebook: VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design; 20th IFIP WG 10.5/IE Andreas Burg,Ay?e Co?kun,Ricardo Reis Conference proc

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Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnectionsber of faults that may occur during the process. In this work, we propose a set of fault-tolerant techniques to cope with faulty wires in Network-on-Chip (NoC). The most appropriate technique is chosen by taking into account the number of faulty wires and their location in the NoC. The goal is to co

Chagrin

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis s, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from pr

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Metastasis

Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates,ncept device and confirmed through simulation. The dynamic, nonvolatile, and concurrent modes of the device are described in detail. Simulations show that the device compares favorably to conventional memory devices. Applications enabled by this unified memory device are discussed, highlighting the

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SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture,to lower memory power using a dual . . in a column-based . . memory with Built-In Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.

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CMOS Implementation of Threshold Gates with Hysteresis,orks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. It will be shown that the new gate style is significantly faster with negligible area and energy overhead.