Titlebook: VLSI-SoC: At the Crossroads of Emerging Trends; 21st IFIP WG 10.5/IE Alex Orailoglu,H. Fatih Ugurdag,Ricardo Reis Conference proceedings 20

overreach

Quantitative Optimization and Early Cost Estimation of Low-Power Hierarchical-Architecture SRAMs Ba quantitative approach provides useful conclusions early in the design phase guiding further optimizations. The estimation error of the power model has been proven to be less than 10?% compared to results based on time-hungry extracted-netlist simulations in a 40-nm CMOS technology.

NAVEN

,Low-Power Low-Voltage ΔΣ Modulator Using Switched-Capacitor Passive Filters,by a partially body-driven technique. The modulator, operated from a 0.7?V supply and clocked with 256?kHz sampling frequency, achieves 84?dB SNR and 80.3?dB SNDR over a 500?Hz signal bandwidth, while it dissipates only 400 nW power.

啟發(fā)

Fine Grain Precision Scaling for Datapath Approximations in Digital Signal Processing Systems,our method to several industrial-strength examples. Our results show a more than 5,000x improvement in optimization time compared to an efficient simulation-based word length optimization method with less than 10?% estimation error across a range of target quality metrics.

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能得到

Enhanced Compressed Look-up-Table Based Real-Time Rectification Hardware, of the compressed look-up-table based rectification algorithm (E-CLUTR) and its novel real-time hardware are presented. E-CLUTR solves more extreme camera alignment and distortion issues than CLUTR while maintaining the low complexity architecture.

寵愛

An FPGA-Based Real-Time System for 3D Stereo Matching, Combining Absolute Differences and Census wied on the justification of dimensioning the system, as well as detailed design and testing information for a fully placed and routed design to process 87 frames per sec (fps) in . resolution, and a fully implemented design for . which runs up?to 1570?fps.

BLAND

Armada

Conference proceedings 2015d. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.

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A Complete Real-Time Feature Extraction and Matching System Based on Semantic Kernels Binarized,een implemented on a Stratix IV FPGA where it delivers a performance of up?to 42 frames per second on 720p video. Especially due to the high throughput of up?to 25?k matched descriptors per frame, our system compares favourably with recent hardware implementations of similar algorithms.