Titlebook: VLSI-SOC: From Systems to Chips; IFIP TC 10/WG 10.5, Manfred Glesner,Ricardo Reis,Hans Eveking Conference proceedings 2006 IFIP Internatio

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Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures,tion. Hardware-based test may reduce the ATE dependency. However, hardware-based test imposes some constraints like area overhead and processing speed degradation. The main objective of this work is to investigate and evaluate a less intrusive test approach called software-based test. Software-based

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Optimizing SOC Test Resources Using Dual Sequences,d annealing based procedure to optimize the SOC test application time and tester resources. The problems we consider are generation of optimal test schedules for SOCs and minimizing tester memory and test channels. Results of experiments conducted on ITC’02 benchmark SOCs show the effectiveness of t

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