Titlebook: VLSI Physical Design: From Graph Partitioning to Timing Closure; Andrew B. Kahng,Jens Lienig,Jin Hu Textbook 20222nd edition The Editor(s)

高度表

Pedagogy

Chip Planning,s. .–.) determines the locations and dimensions of the shapes that are the result of partitioning the entire circuit (Chap. .). Hence, floorplanning produces assigned blocks and enables early estimates of interconnect length, circuit delay, and chip performance. Pin assignment (Sect. .) assigns outg

RALES

Global and Detailed Placement, pin locations (Chap. .), placement seeks to determine the locations of (standard) cells or logic elements within each block. Placement is subject to multiple optimization objectives, a common one being the minimization of the total length of connections between elements. Global placement (Sect. .)

抒情短詩

Global Routing,ng first partitions the chip into routing regions and searches for region-to-region paths for all signal nets; this is followed by detailed routing, which determines the exact tracks and vias of these nets based on their region assignments (Chap. .). During global routing, pins with the same electri

craving

Detailed Routing,c routing tracks, vias, and metal layers in a manner consistent with given global routes of those nets. Traditional detailed routing techniques are applied within routing regions, such as channels (Sect. .) and switch boxes (Sect. .). For modern designs, over-the-cell (OTC) or gcell routing (Sect. .

AUGUR

武器

aquatic

Appendix,hieved in terms of schedule and quality of results, as demonstrated in recent publications (Sect. .). This first part of the appendix identifies a number of useful surveys and reviews ML-based methods that can be applied to tasks addressed in the preceding chapters of the book. Section 9.2 presents

寡頭政治

Textbook 20222nd editionis software needs a?high-level understanding of the underlying mathematical models and algorithms. In?addition, a developer of such software must have a keen understanding of relevant computer?science aspects, including algorithmic performance bottlenecks and how various?algorithms operate and inter

VEN

Netlist and System Partitioning,ts. .–.) can handle large netlists and can redefine a physical hierarchy of an electronic system, ranging from boards to chips, and from chips to blocks. Traditional netlist partitioning can be extended to multilevel partitioning (Sect. .), which can be used to handle large-scale circuits and systems.