Titlebook: VLSI Design and Test; 17th International S Manoj Singh Gaur,Mark Zwolinski,Adit D. Sing Conference proceedings 2013 Springer-Verlag Berlin

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Kapees: A New Tool for Standard Cell Placement,sign that in turn results into minimal routed wire length and thus wire delay. We describe a new method, ., for large scale standard cell placement. Our technique is based on recursive partitioning of placement circuit which is modeled as a hypergraph. It uses partitioning during the global placemen

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Preemptive Test Scheduling for Network-on-Chip Using Particle Swarm Optimization,rallelism and scalability. To reduce the testing cost of such a system, the existing communication structure ca be reused. In this paper, we have proposed a Particle Swarm Optimization (PSO) based mixed test scheduling approach to test the cores in the NoC environment. It incorporates both non-preem

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Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence,tching activity on the address bus of the on-chip data memory, with the help of loop unrolling with partial Gray code sequence. The present work introduces the translation of a loop with array initialization to its loop unrolled version with partial Gray code sequence. The expressions for switching

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Characterization of Logical Effort for Improved Delay,l effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the delay. The validations for minimum delay through simulation was done on a chain of inverters. The improved skewed gates showed 10% - 20% delay reduction on a chain of inverters as compared with normal ske

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A Dual Material Double-Layer Gate Stack Junctionless Transistor for Enhanced Analog Performance,) symmetric double-gate junctionless transistor (DGJLT). The characteristics are demonstrated and compared with dual material gate (DMG) DGJLT and single material (conventional) gate (SMG) DGJLT. DMG DGJLT present superior transconductance (G.), early voltage (V.) and intrinsic gain (G.R.) compared

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