Titlebook: VLSI Design and Test; 22nd International S S. Rajaram,N.B. Balamurugan,Virendra Singh Conference proceedings 2019 Springer Nature Singapore

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High Level Synthesis and Implementation of Cryptographic Algorithm in AHIR Platformription. The existing HLS strategies fails to provide adequate abstraction to the underlying hardware details and thus limits software programmers from designing complex and advanced cipher algorithms. In this paper the method of generating synthesizable Register Transfer Level (RTL) design from alg

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A Hardware Accelerator for Convolutional Neural Network Using Fast Fourier Transformly consists of convolutional layers, max pooling layers, followed by dense fully connected layers. Convolutional layer is the compute intensive layer in CNNs. In this paper we present FFT (Fast Fourier Transform) based convolution technique for accelerating CNN architecture. Computational complexity

CRAB

Reconfigurable VLSI-Architecture of Multi-radix Maximum-A-Posteriori Decoder for New Generation of W levels of power consumption. We have designed major internal blocks of MAP decoder using extensive steering logic to support radix-2/4/8 operating modes. These designs enable efficient clock-gating of our decoder for low-power consumption in different operating modes. This decoder-architecture is p

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A Comparative Exploration About Approximate Full Adders for Error Tolerant Applications the Processors are influenced by the speed and power consumption of arithmetic units. It is improved by adopting approximate computing in arithmetic units with acceptable degradation in the output. Approximate computing is an emerging topic in the past decades, it aims to achieve promising design a

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Optimal Transistor Sizing of Full-Adder Block to Reduce Standby Leakage Poweriques compute optimal transistor sizing for variable operating conditions (temperature, supply voltage) to achieve desirable leakage power and speed for a full-adder circuit. Both techniques use ‘SLEEP’ signal to drive full adder circuit to lower standby mode leakage state without even degrading the

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CMOS Implementations of Rectified Linear Activation Functionsible for this success, improved neural network functionalities, and availability of suitable hardware for training large complex networks. Using these types of novel networks and functions, Deep Neural Networks have been shown to be very highly efficient for various classification tasks. As the nex

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