| 書目名稱 | The Verilog? Hardware Description Language | | 編輯 | Donald E. Thomas,Philip R. Moorby | | 視頻video | http://file.papertrans.cn/922/921992/921992.mp4 | | 圖書封面 |  | | 描述 | The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able | | 出版日期 | Book 1991 | | 關(guān)鍵詞 | Hardware; Verilog; design; simulation | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-3992-6 | | isbn_softcover | 978-1-4613-6784-0 | | isbn_ebook | 978-1-4615-3992-6 | | copyright | Springer Science+Business Media New York 1991 |
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