| 書(shū)目名稱 | System-level Test and Validation of Hardware/Software Systems |
| 編輯 | Matteo Sonza Reorda,Zebo Peng,Massimo Violante |
| 視頻video | http://file.papertrans.cn/885/884559/884559.mp4 |
| 概述 | The reader will learn about the state of the art in system-level validation and test procedures which will enhance both the reliability and performance of system on chip designs |
| 叢書(shū)名稱 | Springer Series in Advanced Microelectronics |
| 圖書(shū)封面 |  |
| 描述 | .New manufacturing technologies have made possible the integration of entire systems on a single chip. This new design paradigm, termed system-on-chip (SOC), together with its associated manufacturing problems, represents a real challenge for designers...SOC is also reshaping approaches to test and validation activities. These are beginning to migrate from the traditional register-transfer or gate levels of abstraction to the system level. Until now, test and validation have not been supported by system-level design tools so designers have lacked the infrastructure to exploit all the benefits stemming from the adoption of the system level of abstraction. Research efforts are already addressing this issue...This monograph provides a state-of-the-art overview of the current validation and test techniques by covering all aspects of the subject including:...modeling of bugs and defects;..stimulus generation for validation and test purposes (including timing errors;..design for testability.. |
| 出版日期 | Book 2005 |
| 關(guān)鍵詞 | Hardware; Microelectronics; System-on-Chip; Validation; microprocessor; modeling; reliability; software; sys |
| 版次 | 1 |
| doi | https://doi.org/10.1007/1-84628-145-8 |
| isbn_softcover | 978-1-84996-953-6 |
| isbn_ebook | 978-1-84628-145-7Series ISSN 1437-0387 Series E-ISSN 2197-6643 |
| issn_series | 1437-0387 |
| copyright | Springer-Verlag London 2005 |
|Archiver|手機(jī)版|小黑屋|
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