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Titlebook: Routing Congestion in VLSI Circuits; Estimation and Optim Prashant Saxena,Rupesh S. Shelar,Sachin S. Sapatne Book 2007 Springer-Verlag US 2

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發(fā)表于 2025-3-21 17:18:55 | 只看該作者 |倒序?yàn)g覽 |閱讀模式
書目名稱Routing Congestion in VLSI Circuits
副標(biāo)題Estimation and Optim
編輯Prashant Saxena,Rupesh S. Shelar,Sachin S. Sapatne
視頻videohttp://file.papertrans.cn/832/831964/831964.mp4
概述Provides an in-depth treatment of routing congestion in VLSI circuits.Comprehensively surveys the work done and points to challenges for the future.Equips readers with the knowledge to prudently choos
叢書名稱Integrated Circuits and Systems
圖書封面Titlebook: Routing Congestion in VLSI Circuits; Estimation and Optim Prashant Saxena,Rupesh S. Shelar,Sachin S. Sapatne Book 2007 Springer-Verlag US 2
描述With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid “tra?c jams”; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a
出版日期Book 2007
關(guān)鍵詞Computer-Aided Design (CAD); Routing; Sapatnekar; VLSI; VLSI circuits; estimation; integrated circuit; metr
版次1
doihttps://doi.org/10.1007/0-387-48550-3
isbn_softcover978-1-4419-4013-1
isbn_ebook978-0-387-48550-8Series ISSN 1558-9412 Series E-ISSN 1558-9420
issn_series 1558-9412
copyrightSpringer-Verlag US 2007
The information of publication is updating

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glish by Thomas Kalary and Frank Schalow.Offers a critical a.Numerous volumes have been written on the philosophy of Martin Heidegger, and new translations of his writings appear on a regular basis. Up to now, however, no book has addressed the connections between Heidegger‘s thought and the hermene
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glish by Thomas Kalary and Frank Schalow.Offers a critical a.Numerous volumes have been written on the philosophy of Martin Heidegger, and new translations of his writings appear on a regular basis. Up to now, however, no book has addressed the connections between Heidegger‘s thought and the hermene
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however, no book has addressed the connections between Heidegger‘s thought and the hermeneutic methodology involved in translating his works - or any other text. Gathering essays by internationally recognized scholars, this volume examines the specific synergy that holds between Heidegger‘s thinking
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however, no book has addressed the connections between Heidegger‘s thought and the hermeneutic methodology involved in translating his works - or any other text. Gathering essays by internationally recognized scholars, this volume examines the specific synergy that holds between Heidegger‘s thinking
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glish by Thomas Kalary and Frank Schalow.Offers a critical a.Numerous volumes have been written on the philosophy of Martin Heidegger, and new translations of his writings appear on a regular basis. Up to now, however, no book has addressed the connections between Heidegger‘s thought and the hermene
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