Titlebook: Recent Issues in Pattern Analysis and Recognition; Virginio Cantoni,Reiner Creutzburg,G. Wolf Book 1989 Springer-Verlag Berlin Heidelberg

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Book 1989ng and measurement of images. It is a selection of refereed papers from two sources: first, a satellite conference within the biannual International Conference on Pattern Recognition held in Rome, November 14-17, 1988, and second, work done at the International Basic Laboratory on Image Processing a

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Data structures and parallel memory organization based on dyadic storage schemes,n advantages over other solutions. They can serve as the basis for the development of parallel memories comprising relatively simple address units and switching networks. The simplicity and the regularity of the control circuits in memories based on the dyadic allocations permit to design the memory with programmable alloctions (structures).

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Image enhancement by path partitioning, output is a partition of the set of pixels into connected regions ("classes"), so that a given set of requirements on the single classes and on adjacent classes is satisfied (i.e. pixels belonging to the same class must have approximately the same grey levels or the same textures and pixels belongi

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An example of integrated circuit design based on silicon compilation: The SCPC1 (Silicon Compiler P tool: a silicon compiler. The new chip is the result of a restructuring of a typical pyramidal architecture previously realized in a more conventional way (see Section I.) The restructuring aim is the creation of a more flexible and modular system exploiting the most important capabilities of a sil

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Bit-level systolic arrays for digital contour smoothing,which improve the already known designs, were suggested. New systolic arrays proposed on the bit level have a simple structure. They consist of single type cells (1-bit full adders), which are separated by 1-bit delay elements. They are suitable for the VLSI implementation.

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Design of bit-level systolic convolvers for image processing,ns with coefficients which are powers of 2. It is then implemented in a two-dimensional bit-level systolic array of full adders. The worst-case space-time requirements of the algorithm involved are superior to the space-time requirements of the systolic convolution algorithms previously known.

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