| 書(shū)目名稱(chēng) | Processor and System-on-Chip Simulation | | 編輯 | Rainer Leupers,Olivier Temam | | 視頻video | http://file.papertrans.cn/760/759089/759089.mp4 | | 概述 | Presents state-of-the-art and future trends in processor and SoC simulation;.Demonstrates how simulation helps to boost hardware and software design productivity;.Addresses simulation requirements and | | 圖書(shū)封面 |  | | 描述 | Simulation of computer architectures has made rapid progress recently. The primary application areas are hardware/software performance estimation and optimization as well as functional and timing verification. Recent, innovative technologies such as retargetable simulator generation, dynamic binary translation, or sampling simulation have enabled widespread use of processor and system-on-chip (SoC) simulation tools in the semiconductor and embedded system industries. Simultaneously, processor and SoC simulation is still a very active research area, e.g. what amounts to higher simulation speed, flexibility, and accuracy/speed trade-offs. This book presents and discusses the principle technologies and state-of-the-art in high-level hardware architecture simulation, both at the processor and the system-on-chip level. | | 出版日期 | Book 2010 | | 關(guān)鍵詞 | EDA; Field Programmable Gate Array; Network on Chip Simulation; Sampling simulation; System on Chip Desi | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4419-6175-4 | | isbn_softcover | 978-1-4899-9607-7 | | isbn_ebook | 978-1-4419-6175-4 | | copyright | Springer Science + Business Media LLC 2010 |
The information of publication is updating
|
|
|Archiver|手機(jī)版|小黑屋|
派博傳思國(guó)際
( 京公網(wǎng)安備110108008328)
GMT+8, 2026-1-24 19:38
發(fā)表于 2025-3-21 19:04:38
