| 書目名稱 | Principles of Verifiable RTL Design |
| 副標(biāo)題 | A functional coding |
| 編輯 | Lionel Bening,Harry Foster |
| 視頻video | http://file.papertrans.cn/756/755847/755847.mp4 |
| 圖書封面 |  |
| 描述 | .Principles of Verifiable RTL Design: A Functional CodingStyle. .Supporting Verification Processes in Verilog. explainshow you can write Verilog to describe chip designs at the RT-level ina manner that cooperates with verification processes. This cooperationcan return an order of magnitude improvement in performance andcapacity from tools such as simulation and equivalence checkers. Itreduces the labor costs of coverage and formal model checking byfacilitating communication between the design engineer and theverification engineer. It also orients the RTL style to provide moreuseful results from the overall verification process. .The intended audience for .Principles of Verifiable RTL Design: A..Functional Coding Style Supporting Verification Processes in..Verilog. is engineers and students who need an introduction tovarious design verification processes and a supporting functionalVerilog RTL coding style. A second intended audience is engineers whohave been through introductory training in Verilog and now want todevelop good RTL writing practices for verification. A third audienceis Verilog language instructors who are using a general text onVerilog as the course textbook but want |
| 出版日期 | Book 2000 |
| 關(guān)鍵詞 | RTL; Verilog; communication; formal verification; logic; model; performance; simulation |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b116517 |
| isbn_softcover | 978-1-4757-7313-2 |
| isbn_ebook | 978-0-306-47016-5 |
| copyright | Springer Science+Business Media New York 2000 |
|Archiver|手機(jī)版|小黑屋|
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