| 書目名稱 | Offset Reduction Techniques in High-Speed Analog-to-Digital Converters |
| 副標題 | Analysis, Design and |
| 編輯 | Pedro M. Figueiredo,Jo?o C. Vital |
| 視頻video | http://file.papertrans.cn/701/700716/700716.mp4 |
| 概述 | All high-speed ADC architectures (flash, two-step, folding and interpolation) covered in detail.The performance parameters and trade-offs encountered in each of the ADC’s sub-blocks are analysed.Most |
| 叢書名稱 | Analog Circuits and Signal Processing |
| 圖書封面 |  |
| 描述 | .Offset Reduction Techniques in High-Speed Analog-to-Digital Converters?.analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed. . |
| 出版日期 | Book 2009 |
| 關鍵詞 | Analog-to-Digital Converter; Averaging; CMOS; Kickback noise; Offset Calibration; design automation |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4020-9716-4 |
| isbn_softcover | 978-90-481-8192-6 |
| isbn_ebook | 978-1-4020-9716-4Series ISSN 1872-082X Series E-ISSN 2197-1854 |
| issn_series | 1872-082X |
| copyright | Springer Science+Business Media B.V. 2009 |