Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing; Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag

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Alessandro Cilardo,Antonino Mazzeo,Luigi Romano,Giacinto Paolo Saggese

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Alan Daly,William Marnane,Tim Kerins,Emanuel Popovici

GRACE

Panacea

Extra-dimensional Island-Style FPGAslike traditionally tiled FPGAs. The proposal uses logical third and fourth dimensions to create increasing wire density for increasing logic capacity. The additional dimensions are mapped to standard two-dimensional silicon. This innovation will increase the longevity of a given cell architecture, a

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Customizable and Reduced Hardware Motion Estimation Processorsully parameterizable 2-D systolic array structure for full-search block-matching motion estimation and inherit its configurability properties in what concerns the macroblock and search area dimensions and parallelism level. A significant reduction of the hardware resources can be achieved with the p

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amplitude

A Unified Codesign Environmentlications. A codesign environment with automatic partitioning and scheduling between a host processor and a number of reconfigurable coprocessors is described. A unified runtime environment for both hardware and software tasks under the control of a task manager is proposed. The practicality of our

freight

Mapping Applications to a Coarse Grain Reconfigurable Systemchitecture, called MONTIUM. The source code is first translated into a control dataflow graph (CDFG). Then after applying graph clustering, scheduling and allocation on this CDFG, it can be mapped onto the target architecture. High performance and low power consumption are achieved by exploiting max