Titlebook: New Algorithms, Architectures and Applications for Reconfigurable Computing; Patrick Lysaght,Wolfgang Rosenstiel Book 2005 Springer-Verlag

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Enabling Run-time Task Relocation on Reconfigurable Systemsware/software context switching issues. The infrastructure proved its feasibility by allowing us to design a relocatable video decoder. When implemented on an embedded platform, the decoder performs at 23 frames/s (320 × 240 pixels, 16 bits per pixel) in reconfigurable hardware and 6 frames/s in software.

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IPsec-Protected Transport of HDTV over IPis highly programmable and can support a variety of offload functions. A sample application is described, wherein production-quality HDTV is transported over IP at nearly 900 Mbps, fully secured using IPsec with AES encryption.

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A Low Energy Data Management for Multi-Context Reconfigurable Architecturesthe reconfigurable architecture. The Data Scheduler attempts to optimally exploit this storage, by deciding in which on-chip memory the data have to be stored in order to reduce energy consumption. We also show that a suitable data scheduling could decrease the energy required to implement the dynamic reconfiguration of the system.