Titlebook: Network and Parallel Computing; 10th IFIP Internatio Ching-Hsien Hsu,Xiaoming Li,Ran Zheng Conference proceedings 2013 IFIP International F

Judicious

和平主義

One-to-One Disjoint Path Covers in DCellns of servers with outstanding network capacity and provide good fault tolerance by only using commodity switches. In this paper, we prove that there exist . vertex disjoint paths {.. | 1?≤?.?≤?.} between any two distinct vertices . and . of .. (.?≥?0) where .?=?.?+?.???1 and . is the vertex number

Override

A Network-Aware Virtual Machine Allocation in Cloud Datacentern which a cloud computing platform runs, are distributed over a wide area network. Therefore, communication cost should be taken into consideration when allocating VMs across servers of multiple datacenters. A network-aware VM allocation algorithm for cloud is developed. It tries to minimize the com

皮薩

Research on the RRB+ Tree for Resource Reservationting. Because the query and update operations of the B+ tree are of high efficiency, so this paper proposes a B+ tree structure suitable for resource reservation the RRB+ tree. Also, we design and implement the corresponding algorithms of query, insertion and deletion. Different with the B+ tree tha

PAEAN

Totoro: A Scalable and Fault-Tolerant Data Center Network by Using Backup Portroposed in the area of parallel computing and structures based on tree hierarchy are not able to satisfy these two demands. In this paper, we propose Totoro, a scalable and fault-tolerant network to handle the challenges by using backup built-in Ethernet ports. We connect a bunch of servers to an in

出來(lái)

偽證

ITC-LM: A Smart Iteration-Termination Criterion Based Live Virtual Machine Migrationnt in virtualized systems. The efficiency of live migration depends on the downtime, total migration time and total transferred data. However, while migrating a memory-intensive VM, XEN/KVM often do many useless iterations of memory copy in order to reach expected downtime which can never be reached

Gorilla

我沒(méi)有強(qiáng)迫

Speeding Up Galois Field Arithmetic on Intel MIC Architectureultiplication tables or discrete logarithms, which limit the speed of its computation. The Intel Many Integrated Core (MIC) Architecture provides 60 cores on chip and very wide 512-bit SIMD instructions, attractive for data intensive applications. This paper demonstrates how to leverage SIMD instruc

Deceit

Analyzing the Characteristics of Memory Subsystem on Two Different 8-Way NUMA Architecturesrns, it shows much different characteristics of memory system between Xeon E5620 with Global Queue and LS 3A with typical crossbar switch. The experiment results reveal the fact that LS 3A and Xeon E5620 have some similar features. Our study also showed some other diverse features of these two platf