| 書(shū)目名稱(chēng) | Nanometer Technology Designs | | 副標(biāo)題 | High-Quality Delay T | | 編輯 | Mohammad Tehranipoor,Nisar Ahmed | | 視頻video | http://file.papertrans.cn/661/660848/660848.mp4 | | 概述 | Identifies defects in traditional at-speed test methods.Proposes new techniques and methodologes to improve the overall quality of transition fault tests.Includes discussion of the effects of IR-drop. | | 圖書(shū)封面 |  | | 描述 | .Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm...Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.. | | 出版日期 | Book 2008 | | 關(guān)鍵詞 | ATPG; at-speed tests; defects; delay; fabrication; high quality; manufacturing; model; nanomanufacturing; nan | | 版次 | 1 | | doi | https://doi.org/10.1007/978-0-387-75728-5 | | isbn_softcover | 978-1-4419-4559-4 | | isbn_ebook | 978-0-387-75728-5 | | copyright | Springer-Verlag US 2008 |
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