| 書(shū)目名稱 | Modeling Microprocessor Performance | | 編輯 | Bibiche Geuskens,Kenneth Rose | | 視頻video | http://file.papertrans.cn/637/636026/636026.mp4 | | 圖書(shū)封面 |  | | 描述 | .Modeling Microprocessor Performance. focuses on thedevelopment of a design and evaluation tool, named RIPE (RensselaerInterconnect Performance Estimator). This tool analyzes the impact onwireability, clock frequency, power dissipation, and the reliabilityof single chip CMOS microprocessors as a function of interconnect,device, circuit, design and architectural parameters. It canaccurately predict the overall performance of existing microprocessorsystems. For the three major microprocessor architectures, DEC,PowerPC and Intel, the results have shown agreement within 10% on keyparameters. .The models cover a broad range of issues that relate to theimplementation and performance of single chip CMOS microprocessors.The book contains a detailed discussion of the various models and theunderlying assumptions based on actual design practices. As such, RIPEand its models provide an insightful tool into single chipmicroprocessor design and its performance aspects. At the same time,it provides design and process engineers with the capability to model,evaluate, compare and optimize single chip microprocessor systemsusing advanced technology and design techniques at an early designstage withou | | 出版日期 | Book 1998 | | 關(guān)鍵詞 | CMOS; development; interconnect; microprocessor; model; modeling; processor; reliability; system; transistor | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4615-5561-2 | | isbn_softcover | 978-1-4613-7543-2 | | isbn_ebook | 978-1-4615-5561-2 | | copyright | Springer Science+Business Media New York 1998 |
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