Titlebook: Memory Issues in Embedded Systems-on-Chip; Optimizations and Ex Preeti Ranjan Panda,Nikil Dutt,Alexandru Nicolau Book 1999 Springer Science

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dition, plenty of figures, computer simulations, biographic details of key mathematicians, and a wealth of examples support and enliven the presentation. .978-1-84800-048-3Series ISSN 0172-5939 Series E-ISSN 2191-6675

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On-Chip vs. Off-Chip Memory: Utilizing Scratch-Pad Memory,ess to their residing data, whereas an access to the off-chip memory (usually DRAM) requires relatively longer access times. The main difference between the Scratch-Pad SRAM and data cache is that, the SRAM guarantees a single-cycle access time, whereas an access to the cache is subject to compulsory, capacity, and conflict misses.

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Background,hus, the first time an instruction or data is accessed, it might have to be fetched from a higher memory level, incurring a relatively higher memory access time penalty. However, it can now be stored in a lower memory level, leading to faster retrieval on subsequent accesses to the same instruction or data.

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Data Organization: The Processor Core/Cache Interface, general purpose architectures available as embedded processors. An example of such a general purpose embedded processor is LSI Logic’s CW4001 [ACG.95], which is based on the MIPS family of processors.

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Introduction,tems-on-Chip (SOC) and Systems-on-Silicon (SOS) are terms used to describe products combining and integrating such megacells onto a single silicon chip; this trend is expected to continue with shrinking feature sizes, and with the capability of embedding DRAMs with logic on the same chip.

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Conclusions,eral new architectural and optimization issues arise in the process of incorporation of these complex components in application-specific embedded systems. In this book, we described techniques for incorporating memory architectures in such embedded systems that contain both custom-synthesized hardware, as well as programmable processor cores.

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