| 書(shū)目名稱(chēng) | Low Power Interconnect Design |
| 編輯 | Sandeep Saini |
| 視頻video | http://file.papertrans.cn/589/588799/588799.mp4 |
| 概述 | Provides practical solutions for delay and power reduction for on-chip interconnects and buses.Focuses on Deep Sub micron technology devices and interconnects.Offers in depth analysis of delay, includ |
| 圖書(shū)封面 |  |
| 描述 | This book provides practical solutions for delay and power reduction for on-chip interconnects and buses.? It provides an in depth description of the problem of signal delay and extra power consumption, possible solutions for delay and glitch removal, while considering the power reduction of the total system.? Coverage focuses on use of the Schmitt Trigger as an alternative approach to buffer insertion for delay and power reduction in VLSI interconnects. In the last section of the book, various bus coding techniques are discussed to minimize delay and power in address and data buses. |
| 出版日期 | Book 2015 |
| 關(guān)鍵詞 | Embedded Systems; Integrated Circuit Design; Interconnect Buffer Insertion; Network on Chip; On-chip int |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4614-1323-3 |
| isbn_softcover | 978-1-4939-4294-7 |
| isbn_ebook | 978-1-4614-1323-3 |
| copyright | Springer Science+Business Media New York 2015 |
|Archiver|手機(jī)版|小黑屋|
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