Titlebook: Low Power Digital CMOS Design; Anantha P. Chandrakasan,Robert W. Brodersen Book 1995 Springer Science+Business Media New York 1995 CMOS.Po

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Book 1995f operations, activity-driven power down, etc.The high- efficiency of DC-DC converter circuitry required forefficient, low-voltage and low-current level operation is described byStratakos, Sullivan and Sanders. The application of various low-powertechniques to a chip set for multimedia applications

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DC Power Supply Design in Portable Systems,ss, with the high efficiency more easily realized in larger converters. A monolithic CMOS DC power supply could meet the severe size and efficiency requirements of a hand-held device. This chapter describes a design methodology for such converters.

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Conclusions,gy is required at all levels of the system design, ranging from the algorithms and architectures to the logic styles, circuits, and underlying technology. An integrated methodology and the associated CAD tools for low power CMOS design has been presented here which incorporates optimization all levels of system design.

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Minimizing Switched Capacitance,citance at all levels of the design. The following sections describe a system level approach to minimize the switched capacitance which involves optimizing algorithms, architectures, logic design, circuit design, and physical design.

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Voltage Scaling Approaches,se which have no advantage in exceeding a bounded computation rate, as found in real-time signal processing. The strategies presented in this chapter also have some applicability to the maximum throughput situation of general purpose computing though additional system level trade-offs must be made.

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Computer Aided Design Tools,arious algorithmic flowgraph transformations, high-level power estimation, and efficient heuristic/probabilistic search mechanisms. While algorithmic transformations have been successfully applied in high-level synthesis with the goal of optimizing speed and/or area, they have not addressed the problem of minimizing power.

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