Titlebook: Logic Synthesis for Field-Programmable Gate Arrays; Rajeev Murgai,Robert K. Brayton,Alberto Sangiovann Book 1995 Springer Science+Business

expeditious

FOR

虛弱

Introductionor. It includes detailed description of the instruction set, the interface with the external world, design objectives and constraints, etc. Then, using years of expertise in integrated-circuit design, they produce an implementation that meets the design objectives. In order to verify that the implem

線

煞費(fèi)苦心

Mapping Combinational Logicting considerations within and pin constraints of a chip. Since it is difficult to incorporate all these factors during synthesis, and only limited success has been achieved so far, for instance, in combining synthesis and routability [82], we approximate this cost by the number of blocks needed. Mi

特征

Logic Optimizationt phase is technology-independent optimization (or logic optimization), in which a . representation of the design is sought. The minimality criterion may be either the number of product terms (if a PLA-like implementation is desired) or the number of literals in a factored form (if a standard-cell i

老人病學(xué)

SPER

訓(xùn)誡

Conclusionsiplexor-based architectures. It was shown that the synthesis problem for these architectures is different from that solved by the conventional, standard-cell based logic synthesis tools. Both logic optimization and technology mapping, the two main steps of the logic synthesis paradigm, need to be mo

libertine