| 書目名稱 | Logic Synthesis for FSM-Based Control Units | | 編輯 | Alexander Barkalov,Larysa Titarenko | | 視頻video | http://file.papertrans.cn/588/587939/587939.mp4 | | 概述 | Presents the hardware implementation of control algorithms represented by graph-schemes of algorithm.Useful for students, practitioners, and researchers in electrical engineering and digital automata | | 叢書名稱 | Lecture Notes in Electrical Engineering | | 圖書封面 |  | | 描述 | .The control unit is one of the most important parts of any digital system responsible for interplay of other system blocks. Very often, the model of a finite state machine (FSM) is used to represent the behaviour of a control unit. Modern computer-aided design tools include a lot of optimal solutions (library cells) for implementation of such regular blocks of digital systems as decoders, multiplexers, parallel multibit adders and so on. But as a rule, control units have an irregular structure which makes impossible to design their logic circuits using the standard library cells. To use these cells, an FSM can be represented by a multilevel model based on the principle of structural decomposition. In multilevel models, for example, multiplexers are used to replace logical conditions, decoders are used to implement microoperations, and different memory blocks are used to transform object codes. ..Design methods depend strongly on such factors as an FSM model in use, specific features of logic elements implementing its logic circuit, characteristics of a control algorithm to be interpreted. In the case of Moore FSM, optimization methods are based on existence of the classes of pseud | | 出版日期 | Book 2009 | | 關鍵詞 | ASIC; Compositional Microprogram Control Units; FPGA; Finite State Machine; Logic Circuit Optimization; L | | 版次 | 1 | | doi | https://doi.org/10.1007/978-3-642-04309-3 | | isbn_softcover | 978-3-642-26064-3 | | isbn_ebook | 978-3-642-04309-3Series ISSN 1876-1100 Series E-ISSN 1876-1119 | | issn_series | 1876-1100 | | copyright | Springer-Verlag Berlin Heidelberg 2009 |
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