Titlebook: Logic Minimization Algorithms for VLSI Synthesis; Robert K. Brayton,Gary D. Hachtel,Alberto L. Sangi Book 1984 Kluwer Academic Publishers

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Multiple-Valued Logic Minimization,As discussed in Chapter 1, many multiple-valued input logic functions can be implemented very efficiently in PLA’s with two-bit input decoders. Hence multiple-valued logic minimization is of great practical importance [FLE 75]. A two-bit decoder pairs two Boolean variables, say x. and x., and generates four decodes

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Logic Minimization Algorithms for VLSI Synthesis978-1-4613-2821-6Series ISSN 0893-3405

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