| 書目名稱 | Latchup in CMOS Technology | | 副標(biāo)題 | The Problem and Its | | 編輯 | Ronald R. Troutman | | 視頻video | http://file.papertrans.cn/582/581754/581754.mp4 | | 叢書名稱 | The Springer International Series in Engineering and Computer Science | | 圖書封面 |  | | 描述 | Why a book on Iatchup? Latchup has been, and continues to be, a potentially serious CMOS reliability concern. This concern is becoming more widespread with the ascendency of CMOS as the dominant VLSI technology, particularly as parasitic bipolar characteristics continue to improve at ever smaller dimensions on silicon wafers with ever lower defect densities. Although many successful parts have been marketed, latchup solutions have often been ad hoc. Although latchup avoidance techniques have been previously itemized, there has been little quantitative evaluation of prior latchup fixes. What is needed is a more general, more systematic treatment of the latchup problem. Because of the wide variety of CMOS technologies and the long term interest in latchup, some overall guiding principles are needed. Appreciating the variety of possible triggering mechanisms is key to a real understanding of latchup. This work reviews the origin of each and its effect on the parasitic structure. Each triggering mechanism is classified according to a new taxonomy. | | 出版日期 | Book 1986 | | 關(guān)鍵詞 | CMOS; Potential; VLSI; Wafer; stability | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4757-1887-4 | | isbn_softcover | 978-1-4419-5199-1 | | isbn_ebook | 978-1-4757-1887-4Series ISSN 0893-3405 | | issn_series | 0893-3405 | | copyright | Springer-Verlag US 1986 |
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