| 書目名稱 | Integrated System-Level Modeling of Network-on-Chip enabled Multi-Processor Platforms |
| 編輯 | Tim Kogel,Rainer Leupers,Heinrich Meyr |
| 視頻video | http://file.papertrans.cn/469/468662/468662.mp4 |
| 概述 | General introduction to SoC platform design and ESL design methodologies.Comprehensive overview of the state-of-the-art research on ESL design.Latest update on SystemC Transaction Level Modeling and s |
| 圖書封面 |  |
| 描述 | We are presently observing a paradigm change in designing complex SoC as it occurs roughly every twelve years due to the exponentially increasing number of transistors on a chip. This design discontinuity, as all previous ones, is characterized by a move to a higher level of abstraction. This is required to cope with the rapidly increasing design costs. While the present paradigm change shares the move to a higher level of abstraction with all previous ones, there exists also a key difference. For the ?rst time shrinking geometries do not leadtoacorrespondingincreaseofperformance. InarecenttalkLisaSuofIBM pointed out that in 65nm technology only about 25% of performance increase can be attributed to scaling geometries while the lion share is due to innovative processor architecture [1]. We believe that this fact will revolutionize the entire semiconductor industry. What is the reason for the end of the traditional view of Moore’s law? It is instructive to look at the major drivers of the semiconductor industry: wireless communications and multimedia. Both areas are characterized by a rapidly increasingdemandofcomputationalpowerinordertoprocessthesophisticated algorithmsnecessarytoo |
| 出版日期 | Book 2006 |
| 關(guān)鍵詞 | Augmented Reality; Electronic System Level (ESL); Multi-Processor System-on-Chip (MP-SoC); Network-on-C |
| 版次 | 1 |
| doi | https://doi.org/10.1007/1-4020-4826-2 |
| isbn_softcover | 978-90-481-7202-3 |
| isbn_ebook | 978-1-4020-4826-5 |
| copyright | Springer Science+Business Media B.V. 2006 |
|Archiver|手機版|小黑屋|
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