Titlebook: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation; 12th International W Bertrand Hochet,Antonio J. Acosta,M

用肘

MDSP: A High-Performance Low-Power DSP Architectureends the standard control-flow DSP architecture with simple data-flow primitives. Such primitives are used to generate concurrent processes at run-time, which independently generate and consume data without accessing the instruction flow. We have evaluated the MDSP proposal by designing an asynchron

陳腐思想

Impact of Technology in Power-Grid-Induced Noiseult, the power supply current delivered through the on-chip power grid is increasing dramatically, which is recognized in the International Technology Roadmap for Semiconductors as a difficult challenge. Early power grid design and the addition of decoupling capacitance have become crucially importa

vasculitis

Exploiting Metal Layer Characteristics for Low-Power Routinges due to increasing design complexities wire capacitance has become dominant over gate capacitance. However the wire load of a net not only depends on wirelength but also on which metal layer a net is routed. In this paper we investigate the characteristics of metal layers and propose a power drive

迎合

Crosstalk Measurement Technique for CMOS ICsrosstalk-induced noise possibility [.], we present a specific test structure to measure crosstalk signal on interconnect lines.An original implementation is proposed for direct amplitude and pulse width measurement of the crosstalk-induced parasitic signal. A validation is given with an HSPICE simul

不容置疑

臭了生氣

Low-Power Asynchronous A/D Conversiony global clock, based on an asynchronous design. Samples conversion is only triggered by the analog input signal amplitude variations, hence an irregular sampling of it. System simulations demonstrate that a significative reduction of the circuit activity can be achieved with it. Moreover, such a co

天氣

Optimal Two-Level Delay — Insensitive Implementation of Logic Functionsminimization. We formulated and proved constraints the minimized logic implementation remains delay-insensitive for. Also, we pointed out an existing tool that produces result under constraints formulated. Using this tool we processed several examples and compared implementation complexity with one

離開(kāi)真充足

別名

A New Methodology to Design Low-Power Asynchronous Circuitsorder to achieve this, we introduce a new timing model called Pseudo Delay-Insensitive model. To prove the goodness of this model, we present the results after comparing, for a set of benchmarks, our implementation with other implementations (synchronous and asynchronous).

弄皺

Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Libraryal design-flow based on an adiabatic standard-cell library and semiautomatic tools allow the quick and easy design and verification of a complex adiabatic system, without loosing the energy reduction benefits. The methodology has been applied to the design of positive feedback adiabatic logic (PFAL)