| 書目名稱 | Instruction Level Parallelism |
| 編輯 | Alex Aiken,Utpal Banerjee,Alexandru Nicolau |
| 視頻video | http://file.papertrans.cn/469/468082/468082.mp4 |
| 概述 | Presents an unprecedented text, uniquely dedicated to Instruction Level Parallelism (ILP).Provides a detailed examination of ILP architectures.Offers practical descriptions of key scheduling algorithm |
| 圖書封面 |  |
| 描述 | This book precisely formulates and simplifies the presentation of Instruction Level Parallelism (ILP) compilation techniques. It uniquely offers consistent and uniform descriptions of the code transformations involved. Due to the ubiquitous nature of ILP in virtually every processor built today, from general purpose CPUs to application-specific and embedded processors, this book is useful to the student, the practitioner and also the researcher of advanced compilation techniques. With an emphasis on fine-grain instruction level parallelism, this book will also prove interesting to researchers and students of parallelism at large, in as much as the techniques described yield insights that go beyond superscalar and VLIW (Very Long Instruction Word) machines compilation and are more widely applicable to optimizing compilers in general. ILP techniques have found wide and crucial application in Design Automation, where they have been used extensively in the optimization of performanceas well as area and power minimization of computer designs.. |
| 出版日期 | Book 2016 |
| 關鍵詞 | Parallelism; Instruction-level parallelism; VLIW; Superscalar; Loop parallelization; Compilers; Optimizati |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4899-7797-7 |
| isbn_softcover | 978-1-4939-7959-2 |
| isbn_ebook | 978-1-4899-7797-7 |
| copyright | Springer-Verlag US 2016 |
|Archiver|手機版|小黑屋|
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