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Titlebook: Innovations in the Memory System; Rajeev Balasubramonian Book 2019 Springer Nature Switzerland AG 2019

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發(fā)表于 2025-3-21 19:24:05 | 只看該作者 |倒序瀏覽 |閱讀模式
書目名稱Innovations in the Memory System
編輯Rajeev Balasubramonian
視頻videohttp://file.papertrans.cn/468/467200/467200.mp4
叢書名稱Synthesis Lectures on Computer Architecture
圖書封面Titlebook: Innovations in the Memory System;  Rajeev Balasubramonian Book 2019 Springer Nature Switzerland AG 2019
描述The memory system has the potential to be a hub for future innovation. While conventional memory systems focused primarily on high density, other memory system metrics like energy, security, and reliability are grabbing modern research headlines. With processor performance stagnating, it is also time to consider new programming models that move some application computations into the memory system. This, in turn, will lead to feature-rich memory systems with new interfaces. The past decade has seen a number of memory system innovations that point to this future where the memory system will be much more than dense rows of unintelligent bits. This book takes a tour through recent and prominent research works, touching upon new DRAM chip designs and technologies, near data processing approaches, new memory channel architectures, techniques to tolerate the overheads of refresh and fault tolerance, security attacks and mitigations, and memory scheduling.
出版日期Book 2019
版次1
doihttps://doi.org/10.1007/978-3-031-01763-6
isbn_softcover978-3-031-00635-7
isbn_ebook978-3-031-01763-6Series ISSN 1935-3235 Series E-ISSN 1935-3243
issn_series 1935-3235
copyrightSpringer Nature Switzerland AG 2019
The information of publication is updating

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Synthesis Lectures on Computer Architecturehttp://image.papertrans.cn/i/image/467200.jpg
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Data Placement,Many factors impact the performance and energy efficiency of off-chip DRAM systems—DRAM timing parameters, parallelism, and row buffer locality. Therefore, smart data placement within DRAM, that in turn impacts timing and locality, is important and is covered in Section 5.1. Data compression deserves its own discussion in Section 5.2.
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Memory Chip Microarchitectures, to poke and prod, and suggest alternative designs. You’d receive the stern “You think we didn’t consider that?” look. A DRAM designer’s look would be even more stern: “We operate at very tight margins and you think we didn’t consider that?!”
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發(fā)表于 2025-3-23 06:38:40 | 只看該作者
Memory Reliability, trillion of these cells in a server, and hundreds of servers in a supercomputer, and the chances of a bit-flip are non-trivial. Therefore, memory is typically protected with redundant error correction codes (ECC) that take care of both error detection and recovery.
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