Titlebook: Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors; José Rodrigo Azambuja,Fernanda Kastensmidt,Jürgen Bo

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書(shū)目名稱Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors影響因子(影響力)




書(shū)目名稱Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors影響因子(影響力)學(xué)科排名




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書(shū)目名稱Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors網(wǎng)絡(luò)公開(kāi)度學(xué)科排名




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書(shū)目名稱Hybrid Fault Tolerance Techniques to Detect Transient Faults in Embedded Processors讀者反饋




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乞討

Conclusions and Future Work,ent levels to achieve high fault detection rates. In spite of that, the main disadvantages were the intrusiveness of most of hardware-based and hybrid techniques and the performance degradations and memory overhead of software-based techniques.

頭腦冷靜

guardianship

discuss the best trade-off between software-based and hardware-based techniques and introduce novel hybrid techniques. Proposed techniques increase existing fault detection rates up to 100%, while maintaining low performance overheads in area and application execution time..978-3-319-35997-7978-3-319-06340-9

放氣

Introduction,s and a personal computer can be found in any cell phone. One the other hand, a few things remained the same, such as the old topic on how to give a system the ability to cope with a fault and continue its correct operation, or in other words, fault tolerance.

火光在搖曳

誘拐

廢墟

Book 2014e degradation and increase error detection when associated with applications implemented in embedded processors. ?Coverage begins with an extensive discussion of the current state-of-the-art in fault tolerance techniques.? The authors then discuss the best trade-off between software-based and hardwa

innovation

venous-leak

Fault Tolerance Techniques for Processors,ware-based techniques and (3) hybrid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybrid techniques applied at software level.