| 書(shū)目名稱(chēng) | High-Speed DSP and Analog System Design | | 編輯 | Thanh T. Tran | | 視頻video | http://file.papertrans.cn/427/426754/426754.mp4 | | 概述 | Tips on cost-efficient design and system simulation that minimize late-stage redesign costs and product shipment delays.Emphasis on good high-speed and analog design practices that minimize both compo | | 圖書(shū)封面 |  | | 描述 | High-Speed DSP and Analog System Design is based on the author’s over 25 years of experience in high-speed DSP and computer systems and courses in both digital and analog systems design at Rice University. It provides hands-on, practical advice for working engineers, including:? Tips on cost-efficient design and system simulation that minimize late-stage redesign costs and product shipment delays ? Emphasis on good high-speed and analog design practices that minimize both component and system noise and ensure system design success.? Guidelines to be used throughout the design process to reduce noise and radiation and to avoid common pitfalls while improve quality and reliability.? Hand-on design examples focusing on audio, video, analog filters, DDR memory, and power supplies.The inclusion of analog systems and related issues cannot be found in other high-speed design books.“This book is an essential resource for all engineers either interested in or working on system designs. It was created by a recognized system design expert who not only teaches these principles daily but who brings years of hands on design expertise as the creator of some of the personal computer industries’ mo | | 出版日期 | Book 20101st edition | | 關(guān)鍵詞 | DDR memory; Electromagnetic Interference; High-speed DSP; Phase-Locked Loop; Printed Circuit Board; analo | | 版次 | 1 | | doi | https://doi.org/10.1007/978-1-4419-6309-3 | | isbn_softcover | 978-1-4899-8337-4 | | isbn_ebook | 978-1-4419-6309-3 | | copyright | Springer Science+Business Media, LLC 2010 |
The information of publication is updating
|
|
|Archiver|手機(jī)版|小黑屋|
派博傳思國(guó)際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-7 05:57
發(fā)表于 2025-3-21 19:39:24
