Titlebook: High Performance Embedded Architectures and Compilers; First International Tom Conte,Nacho Navarro,Theo Ungerer Conference proceedings 200

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Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systemsbedded processor cores, I/O peripherals, a direct memory access (DMA) controller, and off-chip memory. External memory access activities are a major source of energy consumption in embedded systems, and especially in multimedia platforms. In this paper, we focus on the energy dissipated due to the a

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Streaming Sparse Matrix Compression/Decompressionons is described. The proposed architecture seeks to accelerate the key performance-limiting Sparse Matrix-Vector Multiplication (SMVM) operation at the heart of finite-element applications through a combination of a dedicated datapath optimized for these applications with a streaming data-compressi

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Memory-Centric Security Architecturetems designed for the same purpose, the new architecture ties cryptographic properties and security attributes to memory instead of each individual user process. The advantages of such a memory centric design are many folds. First, it provides a better security model and access control on software p

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A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Managementtent. In this paper a HW-solution for group rekeying is proposed. Besides the high performance guaranteed by pipelining and dynamic tree management, the Batch Rekeying Processor enables two modes of operation: real-time and batch rekeying. In addition, our solution uses a new strategy to keep the lo

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