Titlebook: High Performance Embedded Architectures and Compilers; Fourth International André Seznec,Joel Emer,Theo Ungerer Conference proceedings 2009

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A Hardware Task Scheduler for Embedded Video Processingtions. However, software implementations of task scheduling and inter-task synchronization often limit performance improvements of multicores. Remarkably, several demanding video applications (e.g. H.264 video decoding) rely on task dependency graphs that can be constructed from a simple dependency

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MPSoC Design Using Application-Specific Architecturally Visible Communicationions. Producer/consumer relationships map poorly onto cache-based MPSoCs. Instead, we instantiate application specific AVC buffers on top of a distributed consistent and coherent cache-based system with shared main memory to provide the desired functionality. Using JPEG compression as a case study,

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Communication Based Proactive Link Power Managementt issue to the forefront, the issue of chip power consumption, which is projected to increase rapidly with the increase in number of cores. Since NoC infrastructure contributes significantly to the total chip power consumption, reducing NoC power is crucial. While circuit level techniques are import

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