Titlebook: High Level Synthesis of ASICs under Timing and Synchronization Constraints; David C. Ku,Giovanni Micheli Book 1992 Springer Science+Busine

–吃

Behavioral Transformations,final implementation each operation is implemented by a dedicated hardware component. While this assumption may not be realistic due to area and interconnection limits, computing the performance under this assumption is important as a bound on the given behavior.

惡意

Freeze

脖子

存心

使絕緣

Design Space Exploration, reasons. First, the size of the dedicated implementation would typically make it impractical. Second, the interconnection delays would probably not be negligible, and therefore the resulting hardware would not be the fastest achievable implementation in practice.

虛度

Relative Control Generation,R89] to distributed control [BCM. 88]. In the simple case where the hardware model either does not contain any data-dependent delay operations or does not support multiple threads of concurrent execution flow, the control logic can be implemented using a microprogrammed controller or a single finite-state machine in a straightforward way.

Negligible

Neuralgia