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Titlebook: Hardware Specification, Verification and Synthesis: Mathematical Aspects; Mathematical Science Miriam Leeser,Geoffrey Brown Conference proc

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書目名稱Hardware Specification, Verification and Synthesis: Mathematical Aspects
副標題Mathematical Science
編輯Miriam Leeser,Geoffrey Brown
視頻videohttp://file.papertrans.cn/425/424198/424198.mp4
叢書名稱Lecture Notes in Computer Science
圖書封面Titlebook: Hardware Specification, Verification and Synthesis: Mathematical Aspects; Mathematical Science Miriam Leeser,Geoffrey Brown Conference proc
描述Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
出版日期Conference proceedings 1990
關鍵詞Hardware; Mikroelektronik; Mikroprozessor; Schaltkreis; Synchronisation; VLSI; Verifikation; complexity; for
版次1
doihttps://doi.org/10.1007/0-387-97226-9
isbn_softcover978-0-387-97226-8
isbn_ebook978-0-387-34801-8Series ISSN 0302-9743 Series E-ISSN 1611-3349
issn_series 0302-9743
copyrightSpringer-Verlag New York 1990
The information of publication is updating

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Verification of synchronous circuits by symbolic logic simulation,ould normally occur when evaluating circuit operation over many combinations of input and initial state. In this paper, we describe our methodology for verifying synchronous circuits using the stack circuit of Mead and Conway as an illustrative example.
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Formalising the design of an SECD chip,cification and abstraction issues that arose at key levels in the verification of the design. The verification is being undertaken in Cambridge HOL. One hard issue (garbage collection) has been left over for a second iteration of the specification and verification.
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