| 書目名稱 | Functional Verification of Programmable Embedded Architectures |
| 副標(biāo)題 | A Top-Down Approach |
| 編輯 | Prabhat Mishra,Nikil D. Dutt |
| 視頻video | http://file.papertrans.cn/350/349838/349838.mp4 |
| 概述 | Includes the latest studies/statistics on both verification complexity and design failures.Provides a complete view of the existing specification languages for programmable architectures.Demonstrates |
| 圖書封面 |  |
| 描述 | It is widely acknowledged that the cost of validation and testing comprises a s- nificant percentage of the overall development costs for electronic systems today, and is expected to escalate sharply in the future. Many studies have shown that up to 70% of the design development time and resources are spent on functional verification. Functional errors manifest themselves very early in the design flow, and unless they are detected up front, they can result in severe consequence- both financially and from a safety viewpoint. Indeed, several recent instances of high-profile functional errors (e. g. , the Pentium FDIV bug) have resulted in - creased attention paid to verifying the functional correctness of designs. Recent efforts have proposed augmenting the traditional RTL simulation-based validation methodology with formal techniques in an attempt to uncover hard-to-find c- ner cases, with the goal of trying to reach RTL functional verification closure. However, what is often not highlighted is the fact that in spite of the tremendous time and effort put into such efforts at the RTL and lower levels of abstraction, the complexity of contemporary embedded systems makes it difficult t |
| 出版日期 | Book 2005 |
| 關(guān)鍵詞 | ADL; Compilers; Design Space Exploration; EDA Tools; Functional Abstraction; SOC Validation; architecture; |
| 版次 | 1 |
| doi | https://doi.org/10.1007/b137514 |
| isbn_softcover | 978-1-4899-7336-8 |
| isbn_ebook | 978-0-387-26399-1 |
| copyright | Springer-Verlag US 2005 |
|Archiver|手機(jī)版|小黑屋|
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