| 書目名稱 | Formal Semantics for VHDL |
| 編輯 | Carlos Delgado Kloos,Peter T. Breuer |
| 視頻video | http://file.papertrans.cn/346/345902/345902.mp4 |
| 叢書名稱 | The Springer International Series in Engineering and Computer Science |
| 圖書封面 |  |
| 描述 | It is recognized that formal design and verification methodsare an important requirement for the attainment of high quality systemdesigns. The field has evolved enormously during the last few years,resulting in the fact that formal design and verification methods arenowadays supported by several tools, both commercial and academic.. If different tools and users are to generate and read the samelanguage then it is necessary that the same semantics is assigned bythem to all constructs and elements of the language. The current IEEEstandard VHDL language reference manual (LRM) tries to define VHDL aswell as possible in a descriptive way, explaining the semantics inEnglish. But rigor and clarity are very hard to maintain in asemantics defined in this way, and that has already given rise to manymisconceptions and contradictory interpretations. . .FormalSemantics for VHDL. is the first book that puts forward a cohesiveset of semantics for the VHDL language. The chapters describe severalsemantics each based on a different underlying formalism: two of themuse Petri nets as target language, and two of them higher order logic.Two use functional concepts, and finally another uses the concept o |
| 出版日期 | Book 1995 |
| 關(guān)鍵詞 | C programming language; Hardware; Hardwarebeschreibungssprache; Standard; System; VHDL; formal method; logi |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-2237-9 |
| isbn_softcover | 978-1-4613-5941-8 |
| isbn_ebook | 978-1-4615-2237-9Series ISSN 0893-3405 |
| issn_series | 0893-3405 |
| copyright | Kluwer Academic Publishers 1995 |
|Archiver|手機(jī)版|小黑屋|
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