| 書目名稱 | Formal Semantics and Proof Techniques for Optimizing VHDL Models |
| 編輯 | Kothanda Umamageswaran,Sheetanshu L. Pandey,Philip |
| 視頻video | http://file.papertrans.cn/346/345901/345901.mp4 |
| 圖書封面 |  |
| 描述 | .Formal Semantics and Proof Techniques for Optimizing VHDLModels. presents a formal model of VHDL that clearly specifies boththe static and dynamic semantics of VHDL. It provides a mathematicalframework for representing VHDL constructs and shows how thoseconstructs can be formally manipulated to reason about VHDL. Thedynamic semantics is presented as a description of what the simulationof VHDL means. In particular it specifies what values the signals of aVHDL description will take if the description were to be executed. Anadvantage of the approach is that the semantic model can be used tovalidate different simulation algorithms. The book also presents anembedding of the dynamic semantics in a proof checker which is thenused to prove equivalences of classes of VHDL descriptions. ..Formal Semantics and Proof Techniques for Optimizing VHDL Models.is written for hardware designers who are interested in the formalsemantics of VHDL. |
| 出版日期 | Book 1999 |
| 關(guān)鍵詞 | Hardware; Hardwarebeschreibungssprache; Mathematica; Signal; VHDL; algorithms; logic; model; semantics; simul |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-5123-2 |
| isbn_softcover | 978-1-4613-7331-5 |
| isbn_ebook | 978-1-4615-5123-2 |
| copyright | Springer Science+Business Media New York 1999 |
|Archiver|手機(jī)版|小黑屋|
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