| 書(shū)目名稱(chēng) | Formal Equivalence Checking and Design Debugging |
| 編輯 | Shi-Yu Huang,Kwang-Ting (Tim) Cheng |
| 視頻video | http://file.papertrans.cn/346/345700/345700.mp4 |
| 叢書(shū)名稱(chēng) | Frontiers in Electronic Testing |
| 圖書(shū)封面 |  |
| 描述 | .Formal Equivalence Checking and Design Debugging. coverstwo major topics in design verification: logic equivalence checkingand design debugging. The first part of the book reviews the designproblems that require logic equivalence checking and describes theunderlying technologies that are used to solve them. Some novelapproaches to the problems of verifying design revisions afterintensive sequential transformations such as retiming are described indetail. .The second part of the book gives a thorough survey of previous andrecent literature on design error diagnosis and design errorcorrection. This part also provides an in-depth analysis of thealgorithms used in two logic debugging software programs, ErrorTracerand AutoFix, developed by the authors. ..From the Foreword:. .`With the adoption of the .static sign-off. approach to verifyingcircuit implementations the application-specific integrated circuit(ASIC) industry will experience the first radical methodologicalrevolution since the adoption of logic synthesis. Equivalence checkingis one of the two critical elements of this methodological revolution.This book is timely for either the designer seeking to betterunderstand the mechan |
| 出版日期 | Book 1998 |
| 關(guān)鍵詞 | ASIC; RTL; algorithms; circuit; computer-aided design (CAD); debugging; diagnosis; integrated circuit; logic |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-1-4615-5693-0 |
| isbn_softcover | 978-1-4613-7606-4 |
| isbn_ebook | 978-1-4615-5693-0Series ISSN 0929-1296 |
| issn_series | 0929-1296 |
| copyright | Springer Science+Business Media New York 1998 |
|Archiver|手機(jī)版|小黑屋|
派博傳思國(guó)際
( 京公網(wǎng)安備110108008328)
GMT+8, 2025-10-11 19:07
發(fā)表于 2025-3-21 16:05:16
