| 書目名稱 | Fault-Tolerance Techniques for SRAM-Based FPGAs | | 編輯 | Fernanda Lima Kastensmidt,Luigi Carro,Ricardo Reis | | 視頻video | http://file.papertrans.cn/342/341496/341496.mp4 | | 概述 | Very few books discuss fault-tolerance techniques for SRAM-based FPGAs.Shows state-of-the-art fault tolerance solutions for FPGAs.Shows fault-tolerance techniques that can be applied in different desi | | 叢書名稱 | Frontiers in Electronic Testing | | 圖書封面 |  | | 描述 | .Fault-tolerance in integrated circuits is not an exclusive concern regarding space designers or highly-reliable application engineers. Rather, designers of next generation products must cope with reduced margin noises due to technological advances. The continuous evolution of the fabrication technology process of semiconductor components, in terms of transistor geometry shrinking, power supply, speed, and logic density, has significantly reduced the reliability of very deep submicron integrated circuits, in face of the various internal and external sources of noise. The very popular Field Programmable Gate Arrays, customizable by SRAM cells, are a consequence of the integrated circuit evolution with millions of memory cells to implement the logic, embedded memories, routing, and more recently with embedded microprocessors cores. These re-programmable systems-on-chip platforms must be fault-tolerant to cope with present days requirements. This book discusses fault-tolerance techniques for SRAM-based Field Programmable Gate Arrays (FPGAs). It starts by showing the model of the problem and the upset effects in the programmable architecture. In the sequence, it shows the main fault to | | 出版日期 | Book 2006 | | 關(guān)鍵詞 | Digital Systems Design; Fault-tolerance; Field Programmable Gate Arrays; Filter; Programmable Logic; ROM; | | 版次 | 1 | | doi | https://doi.org/10.1007/978-0-387-31069-5 | | isbn_softcover | 978-1-4419-4052-0 | | isbn_ebook | 978-0-387-31069-5Series ISSN 0929-1296 | | issn_series | 0929-1296 | | copyright | Springer-Verlag US 2006 |
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