Titlebook: Euro-Par 2010 - Parallel Processing; 16th International E Pasqua D’Ambra,Mario Guarracino,Domenico Talia Conference proceedings 2010 Spring

ingestion

有危險(xiǎn)

,Die Elektronenr?hre als Elektrometer,echniques or OS enhancements that mitigate jitter. Emulating jitter on a large “jitter-free” platform using either synthetic jitter or real traces from commodity OSes has been proposed as one useful mechanism to study scalability behavior under the presence of jitter. However, this requires access t

BUCK

C. Doelter,G. d’Achiardi,M. Hengleinng is based on dynamic measurements of current loads of JVMs and inter-JVM communication link bandwidth. The JVM loads are approximated by observation of the average idle time that threads report to the OS. The current link bandwidth is determined by observation of the performed average number of RM

Corral

Distributed Systems and Algorithmsributions with solid theoretical foundations and experimental validations on production-level parallel and distributed systems were particularly valued. This year, we encouraged submissions proposing intelligent monitoring and diagnosis tools and environments, which can exploit behavior knowledge to

MIRE

Automated Tuning in Parallel Sorting on Multi-core Architecturesave built a sorting library using empirical search and artificial neural network. Our results show that this sorting library could generate the best parallel sorting algorithms for different input sets on both x86 and SPARC multi-core architectures, with a peak speedup of 2.2x and 3.9x, respectively

Nostalgia

Vulnerable

Profile-Driven Selective Program Loadingse study that shows our system achieves more than 80% reduction in the number of pages that are loaded for several HPC applications while causing no performance overhead for reasonably long running programs.

forestry

Characterizing the Impact of Using Spare-Cores on Application Performancee and quantify under what situations its use will not impact application performance. We show that, for current AMD and Intel multi-core processors, spare-cores can be used for substantial computational tasks but can impact application performance when using shared caches or when significantly acces

anticipate

6Applepolish

jitSim: A Simulator for Predicting Scalability of Parallel Applications in Presence of OS Jitterechniques or OS enhancements that mitigate jitter. Emulating jitter on a large “jitter-free” platform using either synthetic jitter or real traces from commodity OSes has been proposed as one useful mechanism to study scalability behavior under the presence of jitter. However, this requires access t