Titlebook: Enhanced Virtual Prototyping; Featuring RISC-V Cas Vladimir Herdt,Daniel Gro?e,Rolf Drechsler Book 2021 The Editor(s) (if applicable) and T

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https://doi.org/10.1057/9780230389694vides support for verification of cyclic state spaces by preventing revisiting symbolic states and therefore making the verification complete. CSS is a complementary technique that tightly integrates the symbolic simulation engine with the SystemC design under verification to drastically boost the v

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https://doi.org/10.1057/9780230274907little effort to integrate peripherals with concolic execution capabilities. The second approach leverages state-of-the-art CGF in combination with VPs to enable a scalable and efficient verification of embedded SW binaries. To guide the fuzzing process the coverage from the embedded SW is combined

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https://doi.org/10.1007/978-1-4615-4251-3 However, this modern VP-based design flow still has weaknesses, in particular due to the significant manual effort involved for verification and analysis tasks which is both time consuming and error prone. This chapter summarizes the main contributions of the book, that strongly enhance the VP-base

描述

Introduction,executable abstract model of the entire Hardware (HW) platform and pre-dominantly created in SystemC TLM (Transaction Level Modeling). In contrast to a traditional design flow, which first builds the HW and then the Software (SW), a VP-based design flow enables parallel development of HW and SW by l

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Preliminaries,), which is the language of choice to create Virtual Prototypes (VPs). Then, the main concepts of the RISC-V Instruction Set Architecture (ISA) are described. RISC-V is used in several evaluations and case studies in this book and is the ISA implemented in our proposed open-source RISC-V based VP. F

寬容

An Open-Source RISC-V Evaluation Platform,the RISC-V ecosystem. The VP provides a 32/64 bit RISC-V core with an essential set of peripherals and support for multi-core simulations. In addition, the VP also provides SW debug (through the Eclipse IDE) and coverage measurement capabilities and supports the FreeRTOS, Zephyr and Linux operating

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Coverage-Guided Testing for Scalable Virtual Prototype Verification,ethods, which may still be susceptible to state space explosion. Compared to the existing simulation-based verification flow this chapter investigates stronger coverage metrics as well as advanced automated test-case generation and refinement techniques. In particular it considers the Data Flow Test