| 書目名稱 | Efficient Test Methodologies for High-Speed Serial Links |
| 編輯 | Dongwoo Hong,Kwang-Ting Cheng |
| 視頻video | http://file.papertrans.cn/304/303010/303010.mp4 |
| 概述 | Overview of the state-of-the-art testing techniques for high-speed serial links.Analysis of clock and data recovery circuits’ characteristics and their effects on system performance.Analysis of jitter |
| 叢書名稱 | Lecture Notes in Electrical Engineering |
| 圖書封面 |  |
| 描述 | .Efficient Test Methodologies for High-Speed Serial Links describes in detail several new and promising techniques for cost-effectively testing high-speed interfaces with a high test coverage. One primary focus of Efficient Test Methodologies for High-Speed Serial Links is on efficient testing methods for jitter and bit-error-rate (BER), which are widely used for quantifying the quality of a communication system. Various analysis as well as experimental results are presented to demonstrate the validity of the presented techniques.. |
| 出版日期 | Book 2010 |
| 關(guān)鍵詞 | BER Estimation; Clock and Data Recovery (CDR); Design-for-Test (DFT); Hardware; High Speed IO Test; Integ |
| 版次 | 1 |
| doi | https://doi.org/10.1007/978-90-481-3443-4 |
| isbn_softcover | 978-94-007-3094-6 |
| isbn_ebook | 978-90-481-3443-4Series ISSN 1876-1100 Series E-ISSN 1876-1119 |
| issn_series | 1876-1100 |
| copyright | Springer Science+Business Media B.V. 2010 |
|Archiver|手機(jī)版|小黑屋|
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